The present invention relates generally to data generators and more specifically to a fast data generator that starts data generation in response to a trigger signal.
Data generators store data patterns in memory and read the data patterns out as parallel data. The parallel data is then processed in a parallel state. However, the reading speed from the memory is not sufficient for higher speed data pattern signals. Therefore, the need for faster data patterns has resulted in the parallel data being read out of memory as parallel data and then converted into serial data to accelerate the data speed. The data generator usually starts data generation according to a trigger signal. The below described data generators fall into this category.
FIG. 1 is a block diagram of a conventional data generator. A clock generator 12 provides continuous clock CLK to a clock gate 14. The clock gate 14 passes the clock CLK according to a trigger signal. A parallel to serial converter 16 operates based on the gated clock. The parallel to serial converter 16 also provides a divided clock that is derived by dividing the gated clock CLK. A data pattern generation circuit 10 works according to the divided clock. The bit number of the parallel data defines a ratio of the division. For example, if the parallel data is four bits, the division ratio is four. The divided clock is also enabled by the trigger signal and then the data pattern generation circuit 10 provides the parallel data according to the trigger signal.
FIG. 2 is a block diagram of another conventional data generator. The same numbers indicate blocks corresponding to those of FIG. 1. A clock generator 12 provides continuous clock CLK to a parallel to serial converter 16. The parallel to serial converter 16 provides a data pattern generation circuit 10 with divided clock that is produced by dividing the clock CLK. The data pattern generation circuit 10 has a trigger input and starts providing parallel data for producing the serial data when it receives a trigger signal. The parallel to serial converter 16 converts the parallel data into serial data.
A circuit for generating pulses according to a trigger signal is disclosed in U.S. Pat. No. 5,430,660. The circuit uses a voltage-controlled oscillator (VCO) according to the trigger signal. However, the circuit cannot provide fast response because it makes the VCO oscillate according to the trigger signal.
Because the clock CLK (or divided clock) is provided after receiving the trigger signal, the phase of the clock is delayed relative to the trigger signal input. One conventional method of removing the delay is to use DLL (Delay Locked Loop) that intentionally delays at most one cycle to align the phases. But the triggered clock CLK and divided clock are not continuous in the example of FIG. 1 since they are gated according to the trigger signal so that the method using the DLL is not applicable.
On the other hand, the example of FIG. 2 uses the continuous clock and continuous divided clock so that the accelerating method using the DLL may be applicable. However, the time between arrival of a trigger signal and the start of the serial data output fluctuates widely because the divided clock decides the starting point for providing the serial data. For example, if the parallel to serial converter 16 performs a four to one conversion, the divided clock has a period that is four times longer than that of the clock CLK from the clock generation circuit 12. This means that the start point of the serial data relative to the trigger signal has uncertainty that is four times as that of the clock period.
Therefore what is desired is to reduce the uncertainty that is some times larger than a period of a clock for serial data while it keeps the advantage of the circuit of FIG. 2 that can use DLL.